High-Level Data Link Control (HDLC)


Overview:-	The HDLC module provides a software based HDLC engine that performs bit-oriented protocol manipulation on the host processor. The technique uses a fast tabular lookup to simulatenously traverse 7 or 8 states of the HDLC state machine and perform 16-bit CCITT CRC calculations. This project provides a module that can be pushed over a Channel Interface (CHI) stream and provides a Communications Data Interface (cdi(7)) that is suitable for linking under LAPD, LAPF, LAPB, V5.2, GR-303, and DPNSS/DASS Data Link multiplexing drivers.

History:-	A Soft-HDLC engine is part of recent driver code for SS7 signalling links. This is a version of the Soft-HDLC engine for use by ISDN and ISDN-related signalling components that use normal HDLC (multiple flags between frames, no FISU/LSSU compression or repetition).

Status:-	This project is in the Testing stage.

Dependencies:-	This project depends on the Channel Interface (CHI) to the X400P-SS7 and X100P-SS7 drivers.

References:-	References for the HDLC project can be found here.

Design:-	The design is identical to the SDT Soft-HDLC design with the exception that FISU/LSSU compression/repetition has been removed and multiple flags are placed between frames. Also, the Soft-HDLC engine idles flags instead of FISUs.

Code:-	Code for the Soft-HDLC driver can be found in the hdlc and cd sub-directories of the strss7 CVS archive code.

Documentation:-	A manual page for the HDLC driver can be found here: hdlc(4).

Test Results:-	Test results have not yet been released.

Release Package:-	The Soft-HDLC driver will be part of the next major release (0.8.4) of the strss7 package.

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